The present invention is related to Field Programmable Gate Array integrated circuits (FPGAs) and, in particular, to FPGAs having nonvolatile memory cells as the programming portion of the programmable interconnect.
The present invention is related to field programmable integrated circuits, especially Field Programmable Gate Arrays (FPGAs), and more particularly, to floating gate MOS transistors used as switching elements in an FPGA. Typically, an FPGA has an array of logic elements and wiring interconnections with many thousands of programmable interconnects so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect, or switch, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection or to set the function or functions of a logic element.
FPGAs use either memory cells or antifuses for the programmable interconnect. Memory cells are reprogrammable and antifuses are programmable only once. One type of memory-cell programmable interconnect is disclosed in U.S. Pat. No. 5,764,096, entitled, "A GENERAL PURPOSE, NON-VOLATILE REPROGRAMMABLE SWITCH," which issued Jun. 9, 1998 by Robert J. Lipp et al. and is assigned to the present assignee. In the FPGA described in the patent, a non-volatile reprogrammable transistor memory (NVM) cell provides a switching function to randomly interconnect FPGA wiring and circuit elements. Basically, an NVM cell has an MOS transistor with a floating gate which may be charged and/or discharged to provide for the non-volatile programmability feature of NVM technologies.
Further improvements and variations of this programmable interconnect are disclosed in U.S. Pat. No. 5,838,040, entitled, "NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH FN TUNNELING IN SENSE," which issued on Nov. 17, 1998 to R. M. Salter, III, et al. and is assigned to the present assignee; and U.S. application. Ser. No. 09/205,876, entitled "IMPROVED NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH PROGRAMMABLE BURIED BITLINE," filed Dec. 4, 1998 by Jack Zezhong Peng et al. and is assigned to the present assignee (Attorney's Docket No. 16333-16). Still other improvements are described in U.S. application. Ser. No. 09/205,678, entitled "NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH PROGRAMMABLE BURIED SOURCE/DRAIN IN SENSE TRANSISTOR," filed Dec. 4, 1998 by Jack Zezhong Peng et al. and is assigned to the present assignee (Attorney's Docket No. 16333-17). The patent and applications are hereby incorporated by reference.
However, the erasing and programming operations of these programmable interconnects still require high voltages (approximately 20 volts) for relatively long periods of time in comparison to the switching times of the FPGA in normal operation. High voltages place stringent requirements on the programming circuits and the high voltages require more valuable area on the integrated circuit substrate than do low voltages. The erase times are directly related to the costs of testing the FPGA. The present invention is directed toward the lowering of voltages and/or times in the erasing operation, which is typically performed on all of the programmable interconnects before programming of selected interconnects is performed.